1. Technical Field
The embodiments described herein relate to semiconductor integrated circuits, and in particular, to an apparatus and method of setting a test mode in a semiconductor integrated circuit that improves adaptability to various environments.
2. Related Art
Generally, a test is needed at some point during production of a conventional semiconductor integrated circuit, since the simulation results obtained during design and the actual chip operation will often be different. In fact, a large number of tests are performed in order to reduce the error rate of the final semiconductor integrated circuits.
The tests are performed by coding a multi-bit test signal set in an MRS (Mode Register Set) circuit. To this end, the semiconductor integrated circuit includes a test mode setting apparatus that codes a multi-bit test signal to generate a multi-bit test code. The test mode setting apparatus includes a plurality of fuse circuits. Then, the plurality of fuse circuits are artificially controlled to set the default values of the multi-bit test code. Semiconductor integrated circuits having various functions and structures require different default values of the test code. Further, as occasion demands, the test code may not be used at all.
In a conventional apparatus for setting a test mode in a semiconductor integrated circuit, one default value is fixed by a fuse circuit. In order to meet the demands of various semiconductor integrated circuits, the individual semiconductor integrated circuits need to have a test mode setting apparatus having a corresponding configuration. But due to the fixed nature of the fuse circuits, conventional test mode setting apparatus have poor adaptability to various semiconductor integrated circuits. Therefore, time and costs for developing and producing the semiconductor integrated circuit are increased.